CMOS imaging sensor (CIS for short) is widely used for its high integration, low power consumption and low cost, such as the application in digital camera equipment. Wherein CIS equipment is used for sensing the light projected to the semiconductor substrate and further utilizing the active pixel array of a photodiode and a transistor in a semiconductor device, thus converting the image mode acquired (such as convert it to a digital signal or electronic signals). The image quality is one of the most important indicators to measure the performance of the CMOS image sensor. It is an effective way to get good image quality that improving the signal-to-noise ratio of the device. We may increase the signal-to-noise ratio by increase the proportion of the active area for collecting light signal in the total chip area (i.e. pixel fill rate) on the layout design. The active area of the photosensitive device and the active area of the control device is separated by trench in the active area morphology of the image sensor pixel unit area. With the increase of pixel fill rate, the size of the isolation trench will decrease because of the increase of the active area size. Problems will occur as the depth to width ratio of the structure is too large when the isolation trench is decreased to a certain extent, such as void or gap.
In order to solve the problem, mature solution at present is patterning the pixel unit area and the logic circuit area outside in the image sensor by using the forming process of the active region twice, so we may control the depth of the isolation trenches in two different regions by the difference in etching time and appropriately reduce the depth of the pixel unit area so as to decrease the depth-to-width ratio of the trench in this area. Thus to solve the problem of insufficient filling in trenches. But such process needs to pattern the active area repeatedly and require additional photomask, and the process is quite complex at the same time, which inevitably increases the manufacturing costs.